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W9425G6JH
12.6 Mode Register Set (MRS) Timing
CLK
CLK
t MRD
CMD
MRS
NEXT CMD
ADD
A0
Register Set data
Burst Length
A2
A1
A0
Sequential
Interleaved
A1
A2
A3
Burst Length
Addressing Mode
0
0
0
0
0
0
1
1
0
1
0
1
Reserved
2
4
8
Reserved
2
4
8
1
0
0
A4
1
1
0
1
1
0
Reserved
Reserved
A5
A6
CAS Latency
1
1
A3
1
Addressing Mode
A7
"0"
Reserved
0
1
Sequential
Interleaved
A8
A9
"0"
DLL Reset
A6
0
A5
0
A4
0
CAS Latency
Reserved
0
0
1
A10
A11
A12
"0"
"0"
"0"
Reserved
0
0
1
1
1
1
1
0
0
1
0
1
0
1
0
2
3
4
Reserved
2.5
BA0
"0"
Mode Register Set
1
1
1
Reserved
or
BA1
"0"
Extended Mode
Register Set
A8
DLL Reset
0
No
* "Reserved" should stay "0" during MRS cycle.
BA1
0
0
1
1
1
BA0
0
1
0
1
Yes
MRS or EMRS
Regular MRS cycle
Extended MRS cycle
Reserved
Publication Release Date: Aug. 27, 2013
- 38 -
Revision A03
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